1/10 march 2002 introduction the st10x167 / st10f168 contains an analog / digital converter with 10-bit resolution, 9.7 s conversion time, a sample & hold circuit on-chip, esd protected analog inputs and a total unadjusted error of 2lsb. an automatic self-calibration adjusts the adc module to changing temperatures or process variations, giving high performance across the whole automotive temperature range. this application note identifies the causes of adc error and gives solutions to optimize adc performance. an appendix reviews the meaning of the terms: resolution, accuracy and intrinsic error. AN1493 application note reducing analog-digital conversion error using st10x167 / st10f168 by andr roger
AN1493 - application note 2/10 table of contents pag e 1 sources of adc error ...................................................................................... 3 1.1 analog input signal error ............................................................................. 3 1.1.1 source internal resistance matching with adc input parameters ............................ 3 1.1.2 errors due to high frequencies from input signal ..................................................... 5 1.2 input overload errors ................................................................................... 5 1.3 reference voltage errors ........................................................................... 5 1.3.1 reference voltage accuracy and absolute tolerance on a conversion result ......... 5 1.3.2 reference voltage accuracy and differential tolerance on conversion results ....... 5 2 how to minimize error....................................................................................... 6 2.1 optimise the input signal ................................................................................ 6 2.2 reduce input overload error ...................................................................... 6 2.3 reference voltage error reduction ....................................................... 7 3 appendix definitions .......................................................................................... 8 4 revision history .................................................................................................. 8 4.1 creation of the application note on the 19th of october 1998 ..... 8 4.2 revision of the application note on the 23rd of january 2002 ....... 8 4.3 revision of the application note on the 14th of march 2002 ........... 9
AN1493 - application note 3/10 1 - sources of adc error sources of adc accuracy error are classified into 3 categories: C analog input signal error C input overload error C reference voltage error each of these categories is described in the following sections. 1.1 - analog input signal error 1.1.1 - source internal resistance matching with adc input parameters analog input signal error can be created by poor matching of the source internal resistance with the adc input parameters, either caused by, C voltage drop in the voltage source resistance due to input leakage current, C or by poor charging of the adc internal capacitance (cin). analog input error can also be caused by noise from the analog input signal. this section describes each of these causes. refer to figure 1 for a schematic of source internal resistance errors. voltage drop in the source resistance: the error generated by the voltage source internal resistance is: for example : a source resistance of 15k w and a specified leakage current (i oz1 ) of 500na will cause a voltage error of 7.5mv or 1.5lsb. refer the latest product datasheet for the value of i oz1 . note: input leakage current is caused by parasitic current at input pin protection; this protection is necessary to protect the device against esd (electrical static discharge) and against overload. figure 1 : source internal resistance errors v s p5.x vin c io r asrc r1 sample c in agnd agnd i oz1 (input leakage current port5): maximum 200 na (test condition: 0.45v AN1493 - application note 4/10 poor charging of the adc internal capacitance: during the sample time, the input capacitance (c io and c in ) must be charged/discharged by the external source. the internal resistance of the source must allow the capacitance to reach its final value before the end of the sample time: if this does not happen, i.e. if the source resistance is mis-matched to the sample time, a voltage loss will occur at the sample and hold stage. this voltage loss causes an accuracy loss when increasing or decreasing the input voltage from vref/2 (hold capacitor is pre-charged to vref/2 before sampling to reduce charge/discharge time). the error is be calcuated by the formula: where: t s = sample time in m s, r = r source + r1 in w , c = c in + c io in m f. for example: since the error is proportional to the difference between v in and vref/2, the effect produces a non-linearity in the conversion of large-amplitude signals. in practice, if t s > 7rc, the maximum error is reduced to < 1/2 lsb (< 0.05%). errors due to noise from the input signal : the sample and hold circuitry is not designed to filter the input analog signal. noise at the input signal will cause input voltage variation and, therefore, accuracy loss. figure 2 : possible error due to input capacitance charging time v in voltage error at time t i vref/2 t s voltage at sample and hold input vref 0 vref/2 v in error max error lsb () 1 2 -- - 1024 e t s rc -------- - C ? ?? =
AN1493 - application note 5/10 1.1.2 - errors due to high frequencies from input signal small but high frequency signal variations can result in big conversion errors : during sampling time, the analog signal is fed to an internal auto-zero circuitry. signal variations (2 opposite transitions at least) during this time can generate auto-zero error. signal variations during sampling time generate excessively high or low conversion results; big variations (ex : 150mv peak to peak variations at 1.5mhz, with a 2.5v offset for 1 m s sampling time) can generates clamped results (0x000h or 0x3ffh). => allthough the sample and hold internal circuitry is integrating signal variations, other internal analog circuitry can be affected by signal transitions during sampling time, => the input analog signal shall always be low pass filtered to ensure that high frequencies are rejected . 1.2 - input overload errors these errors are caused by input overload. during overload, internal protection-diodes sink current to reduce the overload voltage. because of the close proximity of the internal protection-diodes and the adc circuitry, the adc performance is affected. the st10c167 accepts up to 10ma of input overload current while guaranteeing a total unadusjted error (tue) of 2lsb (refer to the product data sheet for values). overload above the specified limit causes adc accuracy loss and may damage the circuit. 1.3 - reference voltage errors the accuracy of the conversion is obviously linked to the accuracy of the reference voltage. 1.3.1 - reference voltage accuracy and absolute tolerance on a conversion result to compute the accuracy on conversion result, the accuracy on the reference voltage must be taken into account. 1.3.2 - reference voltage accuracy and differential tolerance on conversion results for differential computing (ie : difference between conversions), only the stability of the reference voltage is to take into account. when the analog voltage is derived from a voltage regulator, the accuracy on voltage reference is given by the rejection factor of the regulator and the maximum voltage variation that is possible between the 2 conversions. temperature : temperature coupling effect may be neglected if the time between the 2 samples is short compared to the thermal constant. while noise and/or voltage variations are a well known source of error, internal resistance is another source of error from the reference voltage. during the conversion, the adc internal capacitance must be repeatedly charged or discharged. the internal resistance of the reference voltage must allow the capacitance to reach its correct voltage within the conversion time (see figure 2). a mis-match between the conversion time and reference voltage internal resistance will cause accuracy errors. figure 3 : simplified circuit for analog reference voltage v ref r ref v aref v agnd v in p 5.x c ref r in adc
AN1493 - application note 6/10 2 - how to minimize error 2.1 - optimise the input signal there are three possible optimisations : minimise the total source impedance seen by the st10: this means choosing sensors with low output impedance (not always easy for some types of sensor), and minimising the serial resistance of any protection devices between the analog source and the input pin (while still providing a voltage protection level compatible with the circuit specification). match the sample time to the analog source impedance: use the formula that relates sample time to source internal resistance (given in the st10 datasheet) to match the source resistance to one of the available sample times. for example: with a source impedance of 10k w , and given then the minimum sample time is: note: this formula includes a safety factor of 10, therefore, dynamic errors are ? 0.02lsb. also, r asrc is the total source impedance seen by the device and, therefore, includes any protection components. match the sample time to the analog filter cut-off frequency to remove high frequencies : the st10x167/st10f168 sampling time (adc silicon configuration) shall be 5 to 10 times shorter than the period of the cut-off frequency of the low-pass filter on adc input signal. reduce noise at the input pin: add an external rc filter (with attention to the source internal resistance). comput the average value of different samples in the software routine. 2.2 - reduce input overload error because errors are induced from overload current going into/out of the integrated protection diodes, optimisations minimize this current in 3 ways: minimize the overvoltage at the analog source: the possible optimisations depend on the user application, typically, they involve the addition of zener diodes or transils. for component selection, please refer to st-on-line discrete devices / protection circuit data books. minimize the overvoltage at the st10 analog input pins: either, add protection diode(s) or transil(s), or add a serial resistor. caution: the addition of a serial resistor increases the source internal resistance and, therefore, may impact maximum conversion speed. synchronise adc conversion with analog transitions: where possible, avoid carrying out conversions when analog inputs are scheduled to go into overload conditions (at least, during the transition phase). r asrc t ( s 330 ) 0.25 C = t s 330 r asrc 0.25 + () = t s 3380ns min () =
AN1493 - application note 7/10 2.3 - reference voltage error reduction the possible optimisations are : reference voltage noise: noise can be reduced by carefull design, pcb routing and decoupling of the reference voltage: C place the analog source as close as possible to the v aref pin. C avoid routing any high frequency/high amplitude signals near to the analog source. C make sure that the voltage reference source presents a low impedence from dc to well above the max. sampling frequency (1/t c ): see figure 4. figure 4 : analog reference source - impedance characteristics match the reference voltage internal resistance to conversion time: use the formula that relates conversion time to source internal resistance (given in the st10 datasheet) to match the reference voltage to one of the 3 available conversion times. for example: given then the maximum source impedence for t cc of 1200ns is: note: this should hold up to f=10/t c , so if t c ? 20 m s, i z aref i < 7k w , up to 500khz. figure 5 shows a commonly used circuit for the analog reference voltage. figure 5 : typical analog reference circuit 10/t c z aref ? r aref t cc 165 --------- - 0.25 C = r aref 1200 165 ------------ - 0.25 C = 7k w max () = r c v aref z aref = r// v agnd 1 j w c ----------- - ? ??
AN1493 - application note 8/10 3 - appendix - definitions lsb : least significant bit. resolution : defines the smallest input voltage change required to increment the output of the adc between one code and the next adjacent code. resolution is a design parameter rather than a performance specification; it says nothing about accuracy. resolution is either expressed in percent of the full-scale, or in binary bits. accuracy : defines the worst case difference between the actual input voltage and the full-scale weighted equivalent of the binary output code. for st10 devices, the total unadjusted error describes the maximum sum of all errors intrisic to the adc. intrisic errors : are errors intrisic to the adc itself, such as: quantizing error, scale error, offset error, hysteresis error, linearity error. for simplicity and ease of use, the st10 adc specification gives the sum of all intrisic errors (total unadjusted errors). 4 - revision history 4.1 - creation of the application note on the 19th of october 1998 4.2 - revision of the application note on the 23rd of january 2002 page 1 reference AN1493 has been added. page 2 the table of contents reflects the modification of the document. page 3 section 1.1.1 - source internal resistance matching with adc input parameters has been added. page 5 section 1.3.1 - reference voltage accuracy and absolute tolerance on a conversion result and section 1.3.2 - reference voltage accuracy and differential tolerance on conversion results have been added. page 6 the text: " match the sample time to the analog filter cut off frequency... " and " reduce noise at the input pin... " has been replaced by " low-pass filter the analog input signal: to remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at the adc input. the cut-off frequency of this filter must be twice the highest conversion frequency used in the application as described in the formula: - f cut-off = 2 / t c app where t c app is the shorter conversion time used in the application, calculated with the following formula: - t c app = 14 t cc + t s + 4 tcl (= 14 t cc + 2 t sc + 4 tcl). taking into occount the source internal resistance. compute the average value of different samples in the software routine." page 9 the revision history chapter 4 has been created.
AN1493 - application note 9/10 4.3 - revision of the application note on the 14th of march 2002 page 3 figure 1: r asrc and r1 resistor drawing has been corrected , i oz1 leakage current text has been added. page 5 figure 3: r ref and r in resistor drawing has been corrected. page 6 - paragraph " low-pass filter the analog input signal", former text : "to remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at the adc input. the cut-off frequency of this filter must be twice the highest conversion frequency used in the application as described in the formula: - f cut-off = 2 / t c app where t c app is the shorter conversion time used in the application, calculated with the following formula: - t c app = 14 t cc + t s + 4 tcl (= 14 t cc + 2 t sc + 4 tcl). taking into occount the source internal resistance. compute the average value of different samples in the software routine." - has been replaced by two new paragraphs : " match the sample time to the analog filter cut-off frequency to remove high frequencies : the st10x167/st10f168 sampling time (adc silicon configuration) shall be 5 to 10 times shorter than the period of the cut-off frequency of the low-pass filter on adc input signal. reduce noise at the input pin: add an external rc filter (with attention to the source internal resistance). comput the average value of different samples in the software routine." end of the file - 14th of march 2002.
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